rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. a ad9002 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. high speed 8-bit monolithic a /d converter functional block diagram 256 255 128 127 2 1 d e c o d i n g l o g i c l a t c h r r r r/2 r/2 r r overflow inh analog in +v ref ref mid ? ref encode encode gnd hysteresis ? s bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 (msb) overflow ad9002 bit 1 (lsb) features 150 msps encode rate low input capacitance: 17 pf low power: 750 mw ?.2 v single supply mil-std-883 compliant versions available applications radar systems digital oscilloscopes/ate equipment laser/radar warning receivers digital radio electronic warfare (ecm, eccm, esm) communication/signal intelligence general description t he ad9002 is an 8-bit, high speed, analog-to-digital converter. the ad9002 is fabricated in an advanced bipolar process that allows operation at sampling rates in excess of 150 msps. func- tionally, the ad9002 is comprised of 256 parallel comparator stages whose outputs are decoded to drive the ecl compatible output latches. an exceptionally wide, large signal, analog input bandwidth of 160 mhz is due to an innovative comparator design and very close attention to device layout considerations. the wide input bandwidth of the ad9002 allows very accurate acquisition of high speed pulse inputs without an external track-and-hold. the comparator output decoding scheme minimizes false codes, which is critical to high speed linearity. the ad9002 prov ides an external hysteresis control pin that can be used to optimize comparator sensitivity to further improve performance. additionally, the ad9002? low power dissipation of 750 mw makes it usable over the full extended temperature range. the ad9002 also incorporates an overflow bit to indicate overrange inputs. this overflow output can be disabled with the overflow inhibit pin. the ad9002 is available in two grades, one with 0.5 lsb linearity and one with 0.75 lsb linearity. both versions are offered in an industrial grade, ?5 c to +85 c, packaged in a 28-lead dip and a 28-leaded jlcc. the military temperature range devices, ?5 c to +125 c, are available in a ceramic dip package and complies with mil-std-883 class b.
rev. g ? ad9002?pecifications electrical characteristics ad9002ad/aj ad9002bd/bj ad9002sd ad9002td parameter temp min typ max min typ max min typ max min typ max unit resolution 8 888 bits dc accuracy differential linearity 25 c 0.6 0.75 0.4 0.5 0.6 0.75 0.4 0.5 lsb full 1.0 0.75 1.0 0.75 lsb integral linearity 25 c 0.6 1.0 0.4 0.5 0.6 1.0 0.4 0.5 lsb full 1.2 1.2 1.2 1.2 lsb no missing codes full guaranteed guaranteed guaranteed guaranteed initial offset error top of reference ladder 25 c814 814 8 14 8 14 mv full 17 17 17 17 mv bottom of reference ladder 25 c410 410 4 10 4 10 mv full 12 12 12 12 mv offset drift coefficient full 20 20 20 20 v/ c analog input input bias current 1 25 c60 200 60 200 60 200 60 200 a full 200 200 200 200 a input resistance 25 c25 200 25 200 25 200 25 200 k ? input capacitance 25 c1722 1 722 1722 1722 pf large signal bandwidth 2 25 c 160 160 160 160 mhz input slew rate 3 25 c 440 440 440 440 v/ s reference input reference ladder resistance 25 c40 8 0 110 40 80 110 40 80 110 40 80 110 ? ladder temperature coefficient 0.25 0.25 0.25 0.25 ? / c reference input bandwidth 25 c10 10 1 010mhz dynamic performance conversion rate 25 c 125 150 125 150 125 150 125 150 msps aperture delay 25 c 1.3 1.3 1.3 1.3 ns aperture uncertainty (jitter) 25 c15 15 1 515ps output delay (t pd ) 4, 5 25 c 2.5 3.7 5.5 2.5 3.7 5.5 2.5 3.7 5.5 2.5 3.7 5.5 ns transient response 6 25 c6 666ns overvoltage recovery time 7 25 c6 666ns output rise time 4 25 c 3.0 3.0 3.0 3.0 ns output fall time 4 25 c 2.5 2.5 2.5 2.5 ns output time skew 4, 8 25 c 0.6 0.6 0.6 0.6 ns encode input logic ??voltage 4 full ?.1 ?.1 ?.1 ?.1 v logic ??voltage 4 full ?.5 ?.5 ?.5 ?.5 v logic ??current full 150 150 150 150 a logic ??current full 120 120 120 120 a input capacitance 25 c3 333pf encode pulsewidth (low) 9 25 c 1.5 1.5 1.5 1.5 ns encode pulsewidth (high) 9 25 c 1.5 1.5 1.5 1.5 ns overflow inhibit input 0 v input current full 144 300 144 300 144 300 144 300 a ac linearity 10 effective bits 11 25 c 7.6 7.6 7.6 7.6 bits in-band harmonics dc to 1.23 mhz 25 c48 55 4 855 4855 4855 db dc to 9.3 mhz 25 c50 50 5 050db dc to 19.3 mhz 25 c44 44 4 444db signal-to-noise ratio 12 25 c4 6 47.6 46 47.6 46 47.6 46 47.6 db two tone intermod rejection 13 25 c60 60 6 060db digital outputs 4 logic ??voltage full ?.1 ?.1 ?.1 ?.1 v logic ??voltage full ?.5 ?.5 ?.5 ?.5 v power supply 14 supply current (?.2 v) 25 c 145 175 145 175 145 175 145 175 ma full 200 200 200 200 ma nominal power dissipation 25 c 750 750 750 750 mw reference ladder dissipation 25 c50 50 5 050mw power supply rejection ratio 15 25 c 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 mv/v notes 1 measured with ain = 0 v. 2 measured by fft analysis where fundamental is ? dbc. 3 input slew rate derived from rise time (10% to 90%) of full-scale input. 4 outputs terminated through 100 ? to ? v. 5 measured from encode in to data out for lsb only. 6 for full-scale step input, 8-bit accuracy is attained in specified time. 7 recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage. 8 output time skew includes high-to-low and low-to-high transitions as well as bit-to-bit time skew differences. 9 encode signal rise/fall times should be less than 10 ns for normal operation. 10 measured at 125 msps encode rate. 11 analog input frequency = 1.23 mhz. 12 rms signal to rms noise, with 1.23 mhz analog input signal. 13 input signals 1 v p-p @ 1.23 mhz and 1 v p-p @ 2.30 mhz. 14 supplies should remain stable within 5% for normal operation. 15 measured at ?.2 v 5%. specifications subject to change without notice. (? s = ?.2 v, differential reference voltage = 2.0 v, unless otherwise noted.)
rev. g ad9002 ? absolute maximum ratings 1 supply voltage (? s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v analog-to-digital supply voltage differential . . . . . . . . 0.5 v analog input voltage . . . . . . . . . . . . . . . . . . . . ? s to +0.5 v digital input voltage . . . . . . . . . . . . . . . . . . . . . . . ? s to 0 v reference input voltage (+v ref, ?v ref ) 2 . . . ?.5 v to +0.1 v differential reference voltage . . . . . . . . . . . . . . . . . . . . 2.1 v reference midpoint current . . . . . . . . . . . . . . . . . . . . 4 ma encode to encode differential voltage . . . . . . . . . . . 4 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature range ad9002ad/bd/aj/bj . . . . . . . . . . . . . . . ?5 c to +85 c ad9002sd/td . . . . . . . . . . . . . . . . . . . . ?5 c to +125 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature 3 . . . . . . . . . . . . . . . . . . . . . . . . 150 c lead soldering temperature (10 sec) . . . . . . . . . . . . . 300 c notes 1 absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2 +v ref ? ref under all circumstances. 3 maximum junction temperature (t j max) should not exceed 175 c for ceramic packages, and 150 c for plastic packages: t j = pd ( j a ) + t a = pd ( j c ) + t c where pd = power dissipation j a = thermal impedance from junction to ambient ( c/w) j c = thermal impedance from junction to case ( c/w) t a = ambient temperature ( c) t c = case temperature ( c) typical thermal impedances are: ceramic dip ja = 56 c/w; jc = 20 c/w plcc ja = 60 c/w; jc = 19 c/w recommended operating conditions input voltage (v) parameter min nominal max ? s ?.46 ?.20 ?.94 +v ref ? ref 0.0 +0.1 ? ref ?.1 ?.0 +v ref analog input ? ref +v ref explanation of test levels test level i 100% production tested. test level ii 100% production tested at 25 c and sample tested at specified temperatures. test level iii sample tested only. test level iv parameter is guaranteed by design and characterization testing. test level v parameter is a typical value only. test level vi all devices are 100% production tested at 25 c. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. ordering guide package model linearity temperature range option * ad9002ad 0.75 lsb ?5 c to +85 c d-28 ad9002bd 0.50 lsb ?5 c to +85 c d-28 ad9002aj 0.75 lsb ?5 c to +85 c j-28 ad9002bj 0.50 lsb ?5 c to +85 c j-28 ad9002sd/883b 0.75 lsb ?5 c to +125 c d-28 ad9002td/883b 0.50 lsb ?5 c to +125 c d-28 * d = ceramic dip; j = ceramic chip carrier, j-formed leads. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9002 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. g ad9002 ? functional description pin no. mnemonic description 1 digital ground one of four digital ground pins. all digital ground pins should be connected together. 2 overflow inh overflow inhibit controls the data output polarity for overvoltage inputs. t u p n i g o l a n a d e l b a n e w o l f r e v o ) v 2 . 5 r o g n i t a o l f ( d f o8 d 1 w o l f r e v o) d n g ( d e t i b i h n i d f o8 d 1 v n i v + > f e r 0 0 0 0 0 0 0 0 11 1 1 1 1 1 1 1 0 v n i v + f e r x x x x x x x x 0x x x x x x x x 0 3 hysteresis the hysteresis control voltage varies the comparator hysteresis from 0 mv to 10 mv, for a change from ?.2 v to ?.2 v at the hysteresis control pin. normally converted to ?.2 v. 4+v ref the most positive reference voltage for the internal resistor ladder 5 analog input one of two analog input pins. both analog input pins should be connected together. 6 analog ground one of two analog ground pins. both analog ground pins should be connected together. 7 encode noninverted input of the differential encode input. this pin is driven in conjunction with encode . data is latched on the rising edge of the encode signal. 8 encode inverted input of the differential encode input. this pin is driven in conjunction with encode. 9 analog ground one of two analog ground pins. both analog ground pins should be connected together. 10 analog input one of two analog input pins. both analog inputs should be connected together. 11 ? ref the most negative reference voltage for the internal resistor ladder 12 ref mid the midpoint tap on the internal resistor ladder 13 digital ground one of four digital ground pins. all digital ground pins should be connected together. 14 digital ? s one of two negative digital supply pins (nominally ?.2 v). both digital supply pins should be connected together. 15 d1 (lsb) digital data output 16?9 d2?5 digital data output 20 digital ground one of four digital ground pins. all digital ground pins should be connected together. 21, 22 analog ? s one of two negative analog supply pins (nominally ?.2 v). both analog supply pins should be connected together. 23 digital ground one of four digital ground pins. all digital ground pins should be connected together. 24, 25 d6, d7 digital data output 26 d8 (msb) digital data output 27 overflow overflow data output. logic high indicates an input overvoltage (v in > +v ref ) if overflow inh is enabled (overflow enabled, ?.2 v). see overflow inh. 28 digital ? s one of two negative digital supply pins (nominally ?.2 v). both digital supply pins should be connected together. dip top view (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad9002 digital ground ref mid ? ref analog input analog ground encode digital ground overflow inh hysteresis +v ref encode analog ground analog input d1(lsb) d2 d3 d4 d5 digital ground analog ? s digital ? s overflow d8(msb) d7 analog ? s digital ground d6 digital ? s jlcc 25 24 23 22 21 20 19 5 6 7 8 9 1 0 11 18 17 16 15 14 13 12 26 27 28 1 2 3 4 top view (not to scale) d3 d2 d1(lsb) digital ? s ref mid d8(msb) overflow digital ? s digital ground overflow inh hysteresis +v ref d7 d6 digital ground analog ? s digital ground d5 analog input analog ground encode encode analog ground analog input ? ref d4 analog ? s ad9002 digital ground pin designations
rev. g ad9002 ? die dimensions . . . . . 106 mils 114 mils 15 mils ( 2 mils) pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 4 mils 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gold backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . nitride die attach . . . . . . . . . . . . . . . . . . . . . gold eutectic (ceramic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e poxy (plastic) bond wire . . . . . . . . . . 1 mil?.3 mil gold; gold ball bonding t pd aperture delay analog input encode output data n n + 1 n + 2 n ?1 n + 1 n figure 1. timing diagram ad9002 encode encode ?.2v digital output +v ref r r/2 r/2 r ? ref ?.2v ?.2v ?.2v ?.2v comparator cells ref mid analog input ad9002 ad9002 figure 2. input/output circuits overflow inh ad1 ad2 ad3 1k 1k 100 0.1 f hysteresis analog in encode encode ? ref +v ref ground d1 d2 d3 d4 d5 d6 d7 d8 overflow ?.2v 1k 1k 1k 1k 1k 1k 1k 1k ad9002 ?v 0.1 f static burn in dynamic burn in ad1 = 0v ad2 = ecl high ad3 = ecl low ad1 ad2 ad3 0v ?v ecl high ecl low ecl high ecl low all resistors 5% all capacitors 20% all supplies 5% ? s 1k figure 3. burn-in diagram overflow analog input analog ground encode encode analog ground analog input ? ref ref mid digital ground digital ? s d1 (lsb) d2 d3 d4 d5 digital ground analog ? s digital ground d6 d7 d8 (msb) digital ? s digital ground overflow inh hysteresis +v ref figure 4. die layout and mechanical information
rev. g ad9002 ? layout suggestions designs using the ad9002, such as all high speed devices, m ust follow a few basic layout rules to ensure optimum perfor- mance. esse ntially, these guidelines are meant to avoid many of the problems associated with high speed designs. the first require ment is for a substantial ground plane around and under the ad9002. separate ground plane areas for the digital and analog components may be useful, but these separate grounds should be connected together at the ad9002 to avoid the effects of ground loop currents. th e second area that requires an extra degree of attention involves the three r eference inputs, +v ref , ref mid , and ? ref . the +v ref input and the ? ref input should both be driven from a lo w impedance source (note that the +v ref input is typically t ied to analog ground). a low drift amplifier should provide satisfactory results, even over an extended temperature r ange. adjustments at the ref mid input may be useful in improving the integral line arity by correcting any refer ence ladder skews. the application circuit shown below demonstrates a simple and effective means of driving the reference circuit. the reference inputs should be adequately decoupled to ground th rough 0.1 f chip capacitors to limit the effects of system noise on conversion accuracy. the power supply pins must also be de c oupled to ground to improve noise immunity; 0.1 f and 0.01 f chip capacitors are recommended. th e analog input signal is brought into the ad9002 through two separate input pins. it is very important that the two input pins be driven symmetrically with equal length electrical connec- ti ons. otherwise, aperture delay errors may degrade converter performance at high frequencies. application information the ad9002 is compatible with all standard ecl logic families, including 10k and 10kh. 100k ecl logic levels are tempera ture compensated and are therefore compatible with the ad9002 (and most other ecl device families) only over a limited temperature range. to operate at the highest encode rates, the supporting l ogic around the ad9002 will need to be equally fast. whichever ecl logic family is used, special care must be exer cised to keep digital switching noise away from the analog circuits round the ad9002. the two most critical items are digital supply lines and digital ground return. the input capacitance of the ad9002 is an exceptionally low 17 pf. this allows the use of a wide range of input amplifiers, both hybrid and monolithic. to take full advantage of the wide input bandwidth of the ad9002, a hybrid amplifier such as the a d9610 will be required. for those applications that do not require the full input bandwidth of the ad9002, more tradi- tional monolithic amplifiers, such as the ad846, will work very well. overall performance with any amplifier can be improved by inserting a 10 ? resistor in series with the amplifier output. the output data is buffered through the ecl compatible output latches. all data is delayed by one clock cycle, in addition to the latch propagation delay (t pd ), before becoming available at the out puts. both the analog-to-digital conversion cycle and the data transfer to the output latches are triggered on the rising edge of the differential, ecl compatible encode signal (see figure 1). in applications where only a single-ended signal is avail- able, the ad96685, a high speed, ecl voltage comparator, can be employed to generate the d ifferential signals. a ll ecl sig- nals (including the overflow bit) should be terminated prop erly to avoid ringing and reflection. t he ad9002 also incorporates a hysteresis control pin that provides from 0 mv to 10 mv of additional hysteresis in the comparator input stages. adjustments in the hysteresis control voltage may help improve noise immunity and overall performance in harsh environments. the overflow inh pin of the ad9002 determines how the converter handles overrange inputs (ain +v ref ). in the ?nabled?state (floating at ?.2 v), the overflow inh out- put will be at logic high and all other outputs will be at logic l ow for o verrange inputs (return-to-zero operation). in the ?nhibited?state (tied to ground), the overflow inh out put will be at logic low, and all other outputs will be at logic high for overrange inputs (nonreturn-to-zero operation). the ad9002 provides outstanding error rate performance. this is due to tight control of comparator offset matching and a fault tolerant decoding stage. additional improvements in error rate a re possible through the addition of hysteresis (see hysteresis control pin). this level of performance is extremely important in fault sensitive applications, such as digital radio (qam). dramatic improvements in comparator design and construction give the a d9002 excellent dynamic characteristics, especially snr (signal-to-noise ratio). the 160 mhz input bandwidth and low error rate performance give the ad9002 an snr of 48 db with a 1.23 mhz input. high snr performance is par- tic ularly important in wide bandwidth applications, such as pulse signature analysis, commonly performed in advanced radar receivers. 100 2n3906 overflow d8 (msb) d7 d6 d5 d4 d3 d2 d1 (lsb) ?.2d ?.2a 0.01 f 0.1 f 0.1 f 0.01 f encode encode a in a in ? ref +v ref 0.1 f 10 0.1 f ad741 ad9611 ad96685 40 ad9002 equal distance 50 encode input (ground threshold) analog input (0v to 2v) 1k 4k ?5v 1.5k 50 nyquist filter 1.5k figure 5. typical application
rev. g ad9002 ? 150 2n3906 overflow d8(msb) d7 d6 d5 d4 d3 d2 d1(lsb) ?.2d ?.2a 0.01 f 0.1 f 0.1 f 0.01 f encode encode a in a in ? ref +v ref ad741 hos200 ad96687 75 ad9002 * equal distance 2k encode input (ground threshold) analog input 1k 4.3k ?5v 50 ad9768 dac overflow inh 10 f 3.9k 1k 0.1 f ?5v 625 1k ?.2v ad96687 50 0.1 f hysteresis ?.2v 510 0.1 f 510 ?.2v 1k delay 50 0.1 f 0.01 f 90 20 90 line driver 100114 hos100 hos100 linearity output (error waveform) reconstructed output 3.75 50 1k ad96687 ad96687 100114 line driver outputs require 510 pull-down resistors to ?.2v. all other ecl outputs should be terminated to ?v with 100 resistors, unless otherwise specified. register 100151 0.1 f ref mid * contact factory about evaluation board availability 37-pin d connector 880 13k ?5v 1k delay 880 13k ?5v figure 6. ad9002 evaluation circuit analog input frequency (0.1db below full scale) 125 msps encode rate 65 1mhz rms signal-to-noise ratio (db) and harmonic levels (?bc) 60 55 50 45 40 35 30 100mhz third harmonic second harmonic snr 10mhz figure 7. dynamic performance
rev. g ? c00545??/03(g) ad9002 28-lead side-brazed ceramic dual in-line package [sbdip] (d-28) dimensions shown in inches and (millimeters) 28 114 15 0.610 (15.49) 0.580 (12.73) pin 1 0.100 (2.54) max 0.005 (0.13) min seating plane 0.026 (0.66) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.085 (2.16) max 0.200 (5.08) 0.125 (3.18) 0.070 (1.78) 0.030 (0.76) 0.150 (3.81) min 1.490 (37.85) max 0.100 (2.54) 0.620 (15.75) 0.590 (14.99) 0.018 (0.46) 0.008 (0.20) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design 28-lead ceramic chip carrier - j-formed leads [ jlcc] (j-28a) dimensions shown in inches and (millimeters) 0.450 (11.43) 0.410 (10.41) 0.022 (0.56) 0.012 (0.30) 0.125 (3.18) max 0.035 (0.89) 0.025 (0.64) pin 1 4 5 26 25 19 18 12 11 top view 0.460 (11.68) 0.440 (11.18) sq sq 0.050 (1.27) 0.310 (7.87) 0.290 (7.37) pin 1 index 0.055 (1.40) 4 5 26 25 19 18 12 11 bottom view 0.040 (1.02) ref x 45 3 places 0.500 (12.70) 0.480 (12.19) 0.020 (0.51) ref x 45 controlling dimensions are in inches; millimeters dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design revision history location page 5/03?ata sheet changed from rev. f to rev. g. deleted the e-28a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data sheet changed from rev. e to rev. f. edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 outline dimensions
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